The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the development of very large-scale integrated circuits. These complex circuits are often designed as functionally-defined modules that operate on a set of data and then pass that data on for further processing. This communication from such functionally-defined modules can be passed in small or large amounts of data between individual discrete circuits, between integrated circuits within the same chip, and between remotely-located circuits coupled to or within various parts of a system or subsystem. Regardless of the configuration, the communication typically requires closely-controlled interfaces that are designed to ensure that data integrity is maintained while using circuit designs are sensitive to practicable limitations in terms of implementation space and available operating power.
The increased demand for high-powered, high-functioning semiconductor devices has lead to an ever-increasing demand for increasing the speed at which data is passed between the circuit blocks. Typically, these communication applications are implemented using parallel or serial data transmission, and more often via parallel data transmission. In applications using parallel data transmission, a typical implementation would include sending multiple data bits simultaneously across parallel communication paths. Such “parallel bussing” is a well-accepted approach for achieving data transfers at high data rates. For a given data-transmission rate (sometimes established by a clock passed along with the data), the bandwidth, measured in bits-per-second, is equivalent to the data transmission rate times the number of data signals comprising the parallel data interconnect.
A typical system might include a number of modules that interface to and communicate over a parallel data communication line (sometimes referred to as a data channel), for example, in the form of a cable, a backplane circuit, a bus structure internal to a chip, other interconnect, or any combination of such communication media. A sending module transmits data over the bus synchronously with a clock on the sending module. In this manner, the transitions on the parallel signal lines leave the sending module in a synchronous relationship with each other and/or to a clock on the sending module. At the other end of the parallel data interconnect, the receiving module receives the data on the parallel data bus; where the communication arrangement passes a clock signal, the receive clock is typically derived from or is synchronous with the clock on the sending module. The rate at which the data is passed over the parallel signal lines is sometimes referred to as the (parallel) “bus rate.”
In attempting to optimize the efficiency in such systems, it is beneficial to monitor how the data bus and overall communication block are being used. Traditionally, off-board test analyzers and/or built-in event detectors have been used to detect, count or otherwise measure events occurring on the bus. The information gathered from such tools is then evaluated by the system designers for the purpose of improving the design, e.g., board layout or software organization.
For many applications, improving the design in this manner can be burdensome and costly. For instance, the expense associated with the design of systems requiring customized chips does not permit repeatedly cycling through chip-design layouts for the purpose of improving the bus utilization or throughput. Because such chips are customized by functional specifications, e.g., using a hardware-description language (HDL) such as Verilog or VHDL, chip-design layouts are intended to be altered only at the computer simulation stage of the design. After simulation, the chip prototype is validated in silicon but even then unexpected problems are typical. Overcoming these problems involves use of off-board test analyzers and/or built-in event detectors and more iterations of the above process. Unfortunately, due to the highly integrated structure and high operating speeds of such chips, use of off-board test analyzers and/or built-in event detectors can lead to other problems, such as signal timing, noise-coupling and signal-level issues. Repeatedly redesigning and testing, as typically performed, significantly increases the ultimate design time and cost to such a degree that this practice is often intolerable in today's time-sensitive market. Also, built-in event detectors are typically designed simultaneously with the circuit for which they are to monitor; consequently, they are ineffective for monitoring suspect aspects of the circuit that are discovered post-fabrication.
Ways of improving the development of customized chips can lead to improved communication methods and arrangements that find use in a variety of applications. The present invention addresses the need to overcome the above-mentioned deficiencies of customized-chip development and also provides for communication methods and arrangements that are useful for other applications.